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sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? high speed: 12, 15, 20, 25, 35, 45, 55, and 70ns ? battery backup: 2v data retention ? high-performance, low-power cmos double-metal process ? single +5v ( +10%) power supply ? easy memory expansion with ce1\ and ce2 ? all inputs and outputs are ttl compatible options marking ? timing 12ns access -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45 55ns access -55* 70ns access -70* ? package(s) ceramic dip (300 mil) c no. 108 ceramic lcc e c no. 204 ceramic flatpack f no. 302 ? operating temperature ranges industrial (-40 o c to +85 o c) it military (-55 o c to +125 o c) xt ? 2v data retention/low power l *electrical characteristics identical to those provided for the 45ns access devices. pin assignment (top view) available as military specifications ? smd 5962-38294 ? mil-std-883 28-pin dip (c) (300 mil) 28-pin flat pack (f) 28-pin lcc (ec) general description the mt5c6408, 8k x 8 sram, employs high-speed, low-power cmos technology, eliminating the need for clocks or refreshing. these srams have equal access and cycle times. for flexibility in high-speed memory applications, austin semiconductor offers dual chip enables (ce1\, ce2) and output enable (oe\) capability. these enhancements can place the outputs in high-z for additional flexibility in system design. writing to these devices is accomplished when write enable (we\) and ce1\ inputs are both low and ce2 is high. reading is accomplished when we\ and ce2 remain high and ce1\ and oe\ go low. the device offers a reduced power standby mode when disabled. this allows system designs to achieve low standby power requirements. these devices operate from a single +5v power sup- ply and all inputs and outputs are fully ttl compatible. 8k x 8 sram sram memory array for more products and information please visit our web site at www.austinsemiconductor.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq1 dq2 dq3 vss vcc we\ ce2 a8 a9 a11 oe\ a10 ce1\ dq8 dq7 dq6 dq5 dq4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc a12 a7 a6 a5 a4 a3 a2 a1 a0 dq1 dq2 dq3 vss vcc we\ ce2 a8 a9 a11 oe\ a10 ce1\ dq8 dq7 dq6 dq5 dq4 4 3 2 1 28 27 26 12 13 14 15 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 a5 a4 a3 a2 a1 a0 dq0 a8 a9 a11 oe\ a10 ce1\ dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 a6 a7 a12 nc vcc we\ ce2\
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table row decoder 65,536-bit memory array i/o control v cc vss d q 8 d q 1 ce1\ oe\ we\ a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 column decoder a 8 a 9 a 10 a 11 a 12 power down ce2 mode ce1\ ce2 we\ oe\ dq power standby h x x x high-z standby standby x l x x high-z standby read l h h l q active read l h h h high-z active write l h l x d active
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* voltage on any input or dq relative to vss........-0.5v to +7.0v voltage on vcc supply relative to vss.................-0.5v to +7.0v storage temperature.........................................-65 o c to +150 o c power dissipation......................................................................1w max junction temperature..................................................+175 c lead temperature (soldering 10 seconds)........................+260 o c short circuit output current................................................50ma *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (-55 o c < t c < 125 o c; v cc = 5v +10%) capacitance description conditions symbol min max units notes input high (logic 1) voltage v ih 2.2 vcc+0.5 v 1 input low (logic 0) voltage v il -0.5 0.8 v 1, 2 input leakage current 0v v in vcc il i -10 10 m a output leakage current output(s) disabled 0v < v out < vcc il o -10 10 m a output high voltage i oh = -4.0ma v oh 2.4 v 1 output low voltage i ol = 8.0ma v ol 0.4 v 1 sym -12 -15 -20 -25 -35 -45 units notes i cc 180 170 160 155 155 145 ma 3 i sbtsp 40 40 40 40 40 40 ma i sbtlp 30 30 30 30 30 30 ma i sbcsp 20 20 20 20 20 20 ma i sbclp 10 10 10 10 10 10 ma power supply current: standby max ce\ > v ih ; all other inputs < v il or > v ih , v cc = max f = 0 hz ce\ > (v cc -0.2); v cc = max all other inputs < 0.2v or > (v cc - 0.2v), f = 0 hz conditions ce\ < v il ; v cc = max f = max = 1/t rc (min) output open power supply current: operating parameter description conditions sym max units notes input capacitance c i 6pf 4 output capacitance c o 7pf 4 t a = 25 o c, f = 1mhz vcc = 5v
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (note 5) (-55 o c < t c < 125 o c; v cc = 5v +10%) min max min max min max min max min max min max units notes read cycle read cycle time t rc 12 15 20 25 35 45 ns address access time t aa 12 15 20 25 35 45 ns chip enable access time t ace 12 15 20 25 35 45 ns output hold from address change t oh 200033 ns chip enable to output in low-z t lzce 200000 ns7 chip disable to output in high-z t hzce 7 1015151525ns6, 7 output enable access time t aoe 8 1215151520ns output enable to output in low-z t lzoe 000000 ns output disable to output in high-z t hzoe 7 1015153040ns6 write cycle write cycle time t wc 12 15 20 25 35 45 ns chip enable to end of write t cw 10 13 15 20 30 40 ns address valid to end of write t aw 10 13 15 20 30 40 ns address setup time t as 000000 ns address hold from end of write t ah 000000 ns write pulse width t wp 10 13 15 20 30 40 ns data setup time t ds 7 1012151520 ns data hold time t dh 000055 ns write disable to output in low-z t lzwe 200000 ns7 write enable to output in high-z t hzwe 0 7 0 10 0 10 0 15 0 15 0 25 ns 6, 7 description -12 symbol -45 -35 -25 -20 -15
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac test conditions input pulse levels ...................................... vss to 3.0v input rise and fall times ......................................... 5ns input timing reference levels ................................ 1.5v output reference levels ....................................... 1.5v output load ................................. see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. -3v for pulse width < 20ns 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs unloaded, and f = 1 hz. t rc (min) 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t lzce , t lzwe , t lzoe , t hzce , t hzoe and t hzwe are specified with cl = 5pf as in fig. 2. transition is measured 200mv typical from steady state voltage, allowing for actual tester rc time constant. 7. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe and t hzoe is less than t lzoe . 8. we\ is high for read cycle. 9. device is continuously selected. chip enables and output enables are held in their active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. ce2 timing is the same as ce1\ timing. the waveform is inverted. 13. chip enable (ce1\, ce2) and write enable (we\) can initiate and terminate a write cycle. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) 123 1 2 3 1 2 3 123 1 23 4 1 23 4 1 23 4 1234 dont care undefined low vcc data retention waveform description sym min max units notes v cc for retention data v dr 2 --- v data retention current ce\ > (v cc - 0.2v) v in > (v cc - 0.2v) or < 0.2v v cc = 2v i ccdr 300 a chip deselect to data retention time t cdr 0 --- ns 4 operation recovery time t r t rc ns 4, 11 conditions v th = 1.73v q 167 w 30pf v th = 1.73v q 167 w 5pf 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 123456789 123456789 123456789 123456789 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 data retention mode v dr > 2v 4.5v 4.5v v dr t cdr t r v ih v il v cc ce\
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 taa toh trc trc previous data valid valid data valid address dq read cycle no. 1 8, 9 t rc t aa t oh 1234 1 23 4 1234 1234 1 23 4 1 23 4 1234 dont care undefined tpd tpu thzce tace tlzce thzoe tlzoe taoe trc trc data valid ce\ oe\ dq icc read cycle no. 2 7, 8, 10, 12 t rc t aoe t lzoe t hzoe t hzce t lzce t ace t pu t pd
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 note: output enable (oe\) is inactive (high). write cycle no. 2 7, 12, 13 (write enabled controlled) 1234 1 23 4 1 23 4 1234 12345 1 234 5 1 234 5 12345 dont care undefined write cycle no. 1 12 (chip enabled controlled) tdh tds twp1 twp1 tah tcw taw tcw tas twc twc high z data vaild address ce\ we\ d q t wc t aw t as t cw t ah t wp t ds t dh 1234567890123456789012 1234567890123456789012 1 1 1 1 1 123456789012345678901234567890121234567890 123456789012345678901234567890121234567890 1 1 1 1 1 tdh twp1 twp1 tas taw tcw tah tcw twc twc data valid address ce\ we\ d q high-z t dh t ds t wc t aw t ah t cw t as t wp 12345678901234567 1 234567890123456 7 12345678901234567 12 12 12 1 1 1 1 12345678901234567890123 1 234567890123456789012 3 12345678901234567890123 12 1 1 1 1 123456789 123456789 123456789 dq dq
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 mechanical definitions* asi case #108 (package designator c) smd 5962-38294, case outline z note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. s2 a q l e b b2 s1 d e min max a --- 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d --- 1.485 e 0.240 0.310 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 --- s2 0.005 --- symbol 0.100 bsc smd specifications 0.300 bsc ea c
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 * all measurements are in inches. mechanical definitions* asi case #204 (package designator ec) smd 5962-38294, case outline u note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. a a1 d3 min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 b2 d 0.342 0.358 d1 d2 d3 --- 0.358 e 0.540 0.560 e1 e2 e3 --- 0.558 e h l 0.045 0.055 l2 0.075 0.095 symbol smd specifications 0.072 ref 0.200 bsc 0.100 bsc 0.040 ref 0.050 bsc 0.200 bsc 0.400 bsc e d e3 hx45 o e1 l2 b1 d1 l e b2 e2 d2 h x 45 o
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 * all measurements are in inches. mechanical definitions* asi case #302 (package designator f) smd 5962-38294, case outline m l c e2 a q e3 e min max a 0.045 0.115 b 0.015 0.019 c 0.004 0.009 d --- 0.640 e 0.350 0.420 e2 0.180 --- e3 0.030 --- e l 0.250 0.370 q 0.026 0.045 s 0.000 --- symbol smd specifications 0.050 bsc note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. d e b top view s
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c ** options l = 2v data retention/low power ordering information device number package type speed ns options** process device number package type speed ns options** process mt5c6408 c -12 l /* mt5c6408 ec -12 l /* mt5c6408 c -15 l /* mt5c6408 ec -15 l /* mt5c6408 c -20 l /* mt5c6408 ec -20 l /* mt5c6408 c -25 l /* mt5c6408 ec -25 l /* mt5c6408 c -35 l /* mt5c6408 ec -35 l /* mt5c6408 c -45 l /* mt5c6408 ec -45 l /* mt5c6408 c -55 l /* mt5c6408 ec -55 l /* mt5c6408 c -70 l /* mt5c6408 ec -70 l /* device number package type speed ns options** process mt5c6408 f -12 l /* mt5c6408 f -15 l /* mt5c6408 f -20 l /* mt5c6408 f -25 l /* mt5c6408 f -35 l /* mt5c6408 f -45 l /* mt5c6408 f -55 l /* mt5c6408 f -70 l /* example: mt5c6408c-25l/xt example: mt5c6408f-55/883c example: mt5c6408ec-15l/it
sram mt5c6408 austin semiconductor, inc. mt5c6408 rev. 3.0 2/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 asi to dscc part number cross reference* asi package designator c asi part # smd part # mt5c6808c-12/883c 5962-3829447mzx mt5c6808c-12l/883c 5962-3829446mzx mt5c6808c-20/883c 5962-3829458mza mt5c6808c-20l/883c 5962-3829457mza mt5c6808c-25/883c 5962-3829456mza mt5c6808c-25l/883c 5962-3829455mza mt5c6808c-35/883c 5962-3829454mza mt5c6808c-35l/883c 5962-3829453mza mt5c6808c-45/883c 5962-3829452mza mt5c6808c-45l/883c 5962-3829451mza mt5c6808c-55/883c 5962-3829450mza mt5c6808c-55l/883c 5962-3829449mza mt5c6808c-70/883c 5962-3829448mza asi package designator ec asi part # smd part # mt5c6808ec-12/883c 5962-3829447mux mt5c6808ec-12l/883c 5962-3829446mux mt5c6808ec-20/883c 5962-3829458mua mt5c6808ec-20l/883c 5962-3829457mua mt5c6808ec-25/883c 5962-3829456mua mt5c6808ec-25l/883c 5962-3829455mua mt5c6808ec-35/883c 5962-3829454mua mt5c6808ec-35l/883c 5962-3829453mua mt5c6808ec-45/883c 5962-3829452mua mt5c6808ec-45l/883c 5962-3829451mua mt5c6808ec-55/883c 5962-3829450mua mt5c6808ec-55l/883c 5962-3829449mua mt5c6808ec-70/883c 5962-3829448mua asi package designator f asi part # smd part # mt5c6808f-12/883c 5962-3829447mmx mt5c6808f-12l/883c 5962-3829446mmx mt5c6808f-20/883c 5962-3829458mma mt5c6808f-20l/883c 5962-3829457mma mt5c6808f-25/883c 5962-3829456mma mt5c6808f-25l/883c 5962-3829455mma mt5c6808f-35/883c 5962-3829454mma mt5c6808f-35l/883c 5962-3829453mma mt5c6808f-45/883c 5962-3829452mma mt5c6808f-45l/883c 5962-3829451mma mt5c6808f-55/883c 5962-3829450mma mt5c6808f-55l/883c 5962-3829449mma mt5c6808c-70/883c 5962-3829448mza * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.

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